The synchronous methods presently employed in data communications generally and in particular computer communications are under the control of a clock generator or timer. Evasive means are employed in countering interference which is major concern. High-speed computer systems have their upper limits set on performance but their potential is impeded by delays. This is due in part to the necessity of binary coding of alphanumerics. To transmit, receive, store, decode and convert a long train of bits, includes the problems of framing, synchronization, debugging and parity check (all associated with the present synchronous systems). These problems relating to efficiency and control remain unsolved.
The development of reliable communications have been retarded to a large extend by different forms of interference. Present systems rely mainly on evasive means of countering interference. Added circuitry and component parts represent further delays and the evasive methods used are not always an acceptable alternative.
The number of central processing units (CPU""s) being manufactured continues to increase and many are different and incompatible with each other. This effects an area of technology which would otherwise support portability and compatibility of encoded data.
The communication link between computer systems must be provided with an interface which will provide all systems portability and data exchange compatibility with efficiency and control at the highest degree, free from all extraneous signal interference.
This document describes the concepts developed for such an interface. Included are character and digit coded logic (universal language codes).
Several different attempts have been tried to produce asynchronous data transmission systems in which each character is encoded as a single waveform or pulse duration
Prior Art
U.S. Pat. No. 4,584,691 Herr Apr. 22, 1986
Pulse length modulation system in which detection is accomplished by gating a stable local oscillator and detecting the character or numeral using a cycle counter for the local oscillator.
U.S. Pat. No. 5,661,758 M. E. Long Aug. 26, 1997
The patent discloses a method of encoding in which distinct disruptions are selected for each character of data and introduced on a carrier. The start time and duration of the disruption represent the character encoded.
U.S. Pat. No. 5,588,023 K. F. Ho Dec. 24, 1996
A system for transmitting data employing half cycle wavelength. Information is carried in the duration of the wavelength. A wave duration circuit is disclosed in FIG. 111 as employing a switch, a flip flop, a decoder, a 15 bit counter and a 16 bit latch. And active differentiator is disclosed in FIG. 14. The foregoing prior art issued since U.S. Pat. No. 4,188,581 of this invention recognizes the value of one unique pulse or waveform per pulse as an efficient form of data transmission. A schematic of the sensor (outlined) and a proposed schematic for the xe2x80x9cactivexe2x80x9d section are shown.
This is an improvement upon the Signaling System of the U.S. Pat. No. 4,188,581 of this inventor issued Feb. 12, 1980 and involves the design and features of a new computer interface based upon this prior patent. A copy thereof is attached hereto and is incorporated in its entirety by reference. Universal language codes and formulas developed to eliminate any ambiguous readouts are likewise disclosed. The measurements obtained from pulse parameters and the method used for detection are described.
The computer interface was designed primarily for asynchronous pulse code modulation. Pulses received as applied to the interface are rectified and of fixed duration and are sequenced in time, thereby providing the various elements of information required.
Unlike pulse width and pulse duration modulation where each has only one parameter measurement, in pulse code modulation there are three measurements per character, each character being different. Amplitude is not a parameter of concern. For a more complete understanding of pulse code modulation reference should be made to Oppenheimer and Willsky, Published by Prentice Hall, Inc. SIGNALS AND SYSTEMS(copyright)1997.
The method of coding and decoding alphanumerics expands the interface systems range with a xe2x80x9cbank of codesxe2x80x9d vocabulary. There are five Banks of Codes. Code Bank#1, for example has 23 individual codes lettered xe2x80x9cAxe2x80x9d through xe2x80x9cWxe2x80x9d. Each code increases in number and digit length, extending from common Binary to the 46th character of the Fortran IV code of alphanumerics.
The 23 codes marked xe2x80x9cAxe2x80x9d through xe2x80x9cWxe2x80x9d can be combined into a series of 621 single digit byte instructions by switching from one code to another, or codes can be selected individually by the number of instructions required.
The receiving system of this invention typically includes an input stage such as a receiving antenna input device, followed by an asynchronous wide-band receiver in which output is heterodyned through a down converter by a stabilized oscillator. The output of the converter is applied to a wide-bank I.F. (intermediate frequency) amplifier and precedes to an envelope detector for rectification.
A data acquisition sensor section of the computer interface is basically passive and solid state having linear characteristics. It is capable of use with either low or high level signals and requires no synchronization.
A highly selective anti jamming demultiplexer is also disclosed which is an improvement of the system of U.S. Pat. No. 4,188,581 of R. A. Stevenson. The code demultiplexer is also designed for counter measures as an anti-jam device.
A demultiplexer is employed including a transmission line which is terminated in a reflective termination. The transmission line has a plurality of taps, each related in position to detect a particular alphanumerica encoded pulse. Each tap is spaced from the termination distance related to one half of a discrete pulse length in terms of its propagation rate down the medium. Diodes are associated with each tap and are connected to the logic gates for the system. For the Code Bank#1, the total length of the line is 120 nanoseconds, which allows for detection of pulse lengths from 10 N/Sec. to 240 N/Sec.
The improvements to the demultiplexer of this invention over U.S. Pat. No. 4,188,581, include:
1. the presence a differentiator circuit; and
2. A high speed diodexe2x80x94D1.
The differeniator circuit consists of a network of resistors and a capacitor, followed by a high-speed diode. The diode is forward biased by the positive leading edge of the differentiated pulse and conducts. The diode is reversed biased by the negative trailing edge of the same pulse and acts as a very high impedance or open circuit gate, thereby preventing any premature triggering of following logic gates where negative signals might exceed the logic gate thresholds. The prior art is believed to lack this feature and result.
The positive leading edge of the differentiated pulse and the trailing open circuit gate conduct down the demultiplexer line towards the low impedance ground. Upon reaching ground, the positive leading edge reverses polarity and direction. This negative reflective signal and the incident pulse open circuit gate, each traveling at approximately the speed of light, pass the demultiplexer tap simultaneously, from opposite directions, providing an output pulse with a approximately 50% reduction in duration, rise time and fall time, denoting a detected character.
As shown in the drawings to follow, the demultiplexer taps marked xe2x80x9cAxe2x80x9d through xe2x80x9cWxe2x80x9d are the START pulses and represent the 23 individual codes in the code bank. Each START pulse is used to identify the code to be processed and may also provide spacing for bytes and words, and provide synchronization to computer subsystems.
Following the START pulses is the data from the tap marked xe2x80x9cAxe2x80x9d (xe2x80x9cA primexe2x80x9d). For Code Bank#1 the data pulses are of a fixed duration, e.g. increments of 10 N/Sec., and in one embodiment are spaced apart in time representing the various characters in the code. The taps constitute the detection point for the first and second parameters of each character and represent the measurement of duration of a first and second pulse representing each character.
The signals detected at each tap are transferred to a decoder, where each character is detected by the measurement of a third parameter. Parameter 3 is the time measurement between the parameters 1 and 2. The start and the signals detected from the third measurements are transferred through the logic gates and data bus to the computer for conversion into machine code, storage and processing.
In a second embodiment there is no space between characters unless installed as described above. The detected trailing edge of the first pulse is the beginning of the first character, the trailing edge of the second pulse is the end of the first character and the beginning of the second character. The trailing edge of the third pulse is the end of the second character and the beginning of the third character, etc.
Character recognition is accomplished when the leading parameter 1 of one signal is present at a logic gate tap at the same instant that a parameter 2 signal is at the decoder input. When this occurs, both signals add in amplitude. The parameter one signal at the logic gate tap will exceed the logic gate threshold sending a signal through the data bus to the computer for storage, conversion and processing.
Following the start pulse is the data from the tap marked xe2x80x9cAxe2x80x9d (xe2x80x9cA primexe2x80x9d). For Code Bank#1 the data pulses are of fixed 10 N/Sec. difference in durations and thus are spaced apart in time representing the various characters in the code. Point xe2x80x9cAxe2x80x9d is the detection point for the first and second parameters of each character and represent the measurement of duration of a first and second pulse representing each character.
In addition to the coding scheme for information, the system for receiving and decoding information as described above and in more detail below is believed to constitute a truly novel data receiver and decoder.
The system by reason of the coding employed and the detection and decoding features make them both immune to pulse jamming.